Conventional data processing systems may utilize a phase locked loop (PLL) circuit in a clocking subsystem to recover and phase-align a clock signal that may be transmitted from a forwarded clocking domain to a synchronous clocking domain of a data processing system. The PLL is a closed loop frequency control circuit that performs its function by detecting the phase difference between an input clock signal and an output signal generated by a voltage-controlled oscillator (VCO). A problem with the use of a PLL in such an application is that when the input clock signal is applied to the circuit, it may not automatically become operational. That is, there are typically a number of input parameters that must be configured prior to proper operation of the PLL. These parameters may be adjusted with the use of external jumpers that may be changed as process modifications occur with respect to, e.g., an application specific integrated circuit (ASIC) within which the PLL may be embedded. Alternatively, the input parameters may be adjusted by internal logic that does not rely upon proper PLL operation to set and adjust such parameters.
In an application in which a PLL-based clocking subsystem is used in an input/output (I/O) subsystem of a data processing system, the output clock signal from the PLL is used to activate (i.e., clock) logic contained in an I/O interface circuit of the I/O subsystem. The logic contained in the I/O interface between a processor and I/O subsystem is generally non-operational until the clock signals delivered from the PLL are synchronized to enable transmission of commands between the processor and I/O subsystem. A server management subsystem within the data processing system may be unable to initialize any circuits within the I/O interface nor access any registers, e.g., control status registers (CSRS) within that interface without adding unnecessary complexity to the I/O interface and management subsystem.
Another way of initializing the circuitry within the I/O interface involves the use of special signals between the processor and I/O interface. This approach requires the use of different cables to accommodate those signals and, thus, obviates the ability to reuse similar cables between processors, and between processors and I/O subsystems, thereby creating a complicated cabling arrangement. Moreover, data processing systems, such as high performance server computers, typically utilize synchronous clock forwarded interface circuits to provide high data bandwidth on relatively narrow interconnects or links associated with the interface circuits. Clock forwarding is a technique in which data signals are accompanied by clock signals. It is thus desirable to keep the interfaces between the processors and I/O subsystems (in particular the I/O interfaces) similar to thereby enable the use of similar parts, such as cables, in a low cost manner.
The present invention is generally directed to a circuit configured to initialize a PLL within a clocking subsystem upon startup and re-initialize the PLL in the absence (or loss) of forwarded clock signals propagating between a processor and I/O interface. These clock signals may stop propagating as a result of failures in the cable coupling a processor to an I/O interface or faults in the logic circuitry of the I/O interface. All input signals received at the PLL must be preconfigured and stable prior to proper functioning of the PLL, particularly one that is embedded in an ASIC. In addition, the forwarded clock signals received at the PLL must be stable prior to initial startup of the PLL circuit. Therefore, a reset input to the PLL cannot be released until the input clock signal is stable and the other input signals are stable. As a result, the present invention is directed to a technique that enables detection of the forwarded clock signals received at a PLL and that activates (brings up) the PLL in a predetermined sequence that comports with the specifications and requirements of the vendor's PLL.